Integrated circuit (IC) manufacturers test the input/output (I/O) paths of IC chips and packages in order to determine whether or not their products satisfy certain timing specifications. However, current approaches can involve elaborate preparation and provide only an approximation of the actual timing. For example, a System-on-Chip (SOC) product can include a processor subsystem and a programmable logic subsystem having the processor subsystem and the programmable logic subsystem coupled to I/O pads of the SOC via a switch. Testing the delay on the I/O paths from the processor subsystem to the I/O pads can involve creating test programs that execute on the processor subsystem and that write data to and read data from various ones of the I/O pads of the SOC. However, execution of the test programs does not provide sufficient control to determine set-up and hold times for I/O pads on the receive interface of the processor subsystem or the clock-to-out minimum/maximum times to I/O pads from the transmit interface of the processor subsystem.